The present invention generally relates to the transmission of data over a serial data link and more particularly to encoding methods and apparatus for generating DC balanced, run length limited codes for transmission over a serial data link and a decoder for decoding such codes.
Numerous applications exist in which it is desirable to transmit data over a high speed serial data link. Well known problems must be overcome, however, when transmitting data over serial data links at high speed. To maintain a high signal to noise ratio, differential transmitters and receivers are often employed at the transmitting and receiving ends of the serial link. It is well known that it is desirable to maintain the transmitted binary signal generally in a DC balanced state to maintain good common mode rejection characteristics at the receiver. DC balance is maintained by transmitting approximately the same number of binary 1s as 0s over the link. This would not typically occur if data were just randomly transmitted over the serial data link. To obtain a DC balanced signal for transmission over a serial link it is known in the art that encoders and decoders may be employed to assure that a balanced condition is maintained over the link. If transmissions over the serial link are imbalanced (i.e. more binary 1's than 0's or more 0's than 1's) a DC offset may be induced on the serial link which can interfere with the ability of a differential receiver to properly decode the binary digits.
When transmitting data at high speeds over a serial data link it is often impractical or not desirable to provide a separate clock signal for data recovery at the receiver since clock skew may occur. Additionally, it is often desirable to minimize the number of backplane or data link signals and the provision of a separate clock signal necessarily increases the signal count. For this reason, a clock signal is sometimes recovered from the serially transmitted data using a phase locked loop at the receive end of the serial data link. To maintain proper operation of a phase locked loop, however, the input signal to the phase locked loop must exhibit sufficient transitions for the phase locked loop to maintain a lock on the input data frequency. If the received data, for example, comprises a long string of logic 1s or 0s, the absence of transitions renders clock recovery difficult. For this reason, run length limited encoding techniques are employed. A run length limited (RLL) code is an encoded character which has a maximum number of logic 0s or 1s in a row. For example, a digital signal with a run length limit of 5 has a maximum of five consecutive logic 0s or 1s. It is known to select run length limited codes so as to maintain the run length over successive characters. The use of such run length limited encoding technique maintains sufficient clocking transitions to permit clock recovery and recovery of the data stream at the receiver.
A number of encoding techniques have been developed to address the problems associated with the maintenance of DC balance and data stream synchronization using RLL codes. One such technique is disclosed in U.S. Pat. No. 4,486,379 entitled Byte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Code. The encoding circuit therein disclosed partitions an 8 bit byte of information into 5 bit and 3 bit sub-blocks for encoding purposes. The 5 bit and 3 bit blocks are separately encoded while maintaining DC balance across all block and sub-block boundaries.
It would therefore be desirable to be able to provide a simple, cost effective DC balanced encoder/decoder with a short run length limit to provide improved data transmission and clock recovery over a serial data link.